BUAA-CLab/CircuitMind
The code about TC-Bench and CircuitMind
This project helps electrical engineers and hardware designers create highly efficient digital circuits at the gate level. You input design specifications, and it outputs optimized circuit netlists that rival or exceed human expert designs in terms of gate count and delay. It is primarily for logic designers or researchers focused on advanced hardware synthesis.
No commits in the last 6 months.
Use this if you need to automatically generate complex gate-level digital circuits with optimal efficiency for a specific design problem.
Not ideal if you are looking for high-level architectural design tools or don't need highly optimized gate-level implementations.
Stars
8
Forks
2
Language
Python
License
Apache-2.0
Category
Last pushed
Jun 07, 2025
Commits (30d)
0
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