99EnriqueD/verilog_autocompletion
Code implementation for "A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation"
This project helps chip designers and verification engineers write Verilog code more quickly and accurately by suggesting completions as they type. It takes partially written Verilog code as input and provides intelligent, context-aware code suggestions. Engineers working on hardware description and verification tasks would use this to accelerate their development.
No commits in the last 6 months.
Use this if you are a hardware design or verification engineer looking for an AI-powered tool to speed up your Verilog coding.
Not ideal if you are working with hardware description languages other than Verilog or require a production-ready, fully integrated IDE feature.
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8
Forks
2
Language
Jupyter Notebook
License
MIT
Category
Last pushed
Aug 21, 2025
Commits (30d)
0
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