vint-1/chipdiffusion
Chip Placement with Diffusion Models (ICML 2025)
This project helps integrated circuit (IC) designers and layout engineers automatically arrange the components (like logic gates and memory blocks) on a microchip. You input a netlist (the circuit's connectivity) in standard formats like DEF/LEF, and it outputs an optimized physical placement for these components. This speeds up the crucial physical design phase of chip development.
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Use this if you need an automated, advanced method to generate efficient and legal chip placements using state-of-the-art diffusion models, especially for complex designs.
Not ideal if you require a traditional, rule-based placement engine or are not comfortable with machine learning model training and evaluation workflows.
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Last pushed
Jun 27, 2025
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