vint-1/chipdiffusion

Chip Placement with Diffusion Models (ICML 2025)

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Emerging

This project helps integrated circuit (IC) designers and layout engineers automatically arrange the components (like logic gates and memory blocks) on a microchip. You input a netlist (the circuit's connectivity) in standard formats like DEF/LEF, and it outputs an optimized physical placement for these components. This speeds up the crucial physical design phase of chip development.

No commits in the last 6 months.

Use this if you need an automated, advanced method to generate efficient and legal chip placements using state-of-the-art diffusion models, especially for complex designs.

Not ideal if you require a traditional, rule-based placement engine or are not comfortable with machine learning model training and evaluation workflows.

IC-design chip-layout electronic-design-automation physical-design VLSI
No License Stale 6m No Package No Dependents
Maintenance 2 / 25
Adoption 6 / 25
Maturity 7 / 25
Community 15 / 25

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Last pushed

Jun 27, 2025

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