Intelligent-Computing-Research-Group/HaVen
[DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers
HaVen helps hardware description language (HDL) engineers generate accurate Verilog code for digital circuits using large language models (LLMs). It takes natural language descriptions or specifications of a circuit and produces synthesizable Verilog code, minimizing common errors like logical inconsistencies or incorrect syntax. This tool is for HDL engineers who want to accelerate their design process by leveraging AI for code generation.
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Use this if you are an HDL engineer looking to use AI to generate Verilog code and need to ensure the output is reliable, free from common LLM 'hallucinations', and adheres to engineering best practices.
Not ideal if you primarily work with other hardware description languages like VHDL or SystemVerilog, as this tool is specifically designed for Verilog.
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Verilog
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Last pushed
Jul 09, 2025
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