rpjayaraman/RTL2UVM
Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.
This tool helps hardware verification engineers quickly set up Universal Verification Methodology (UVM) testbenches for their Verilog Register Transfer Level (RTL) designs. You provide your Verilog design file, and it automatically generates a complete UVM testbench framework, significantly reducing manual setup time. This is ideal for verification engineers responsible for ensuring the correctness of digital hardware designs.
Use this if you need to rapidly create a comprehensive UVM testbench structure from your Verilog RTL code, with the option to use AI for intelligent test logic.
Not ideal if you need a fully custom, hand-coded UVM testbench from scratch or if you are not working with Verilog RTL designs.
Stars
19
Forks
5
Language
SystemVerilog
License
MIT
Category
Last pushed
Feb 24, 2026
Commits (30d)
0
Get this data via API
curl "https://pt-edge.onrender.com/api/v1/quality/llm-tools/rpjayaraman/RTL2UVM"
Open to everyone — 100 requests/day, no key needed. Get a free key for 1,000/day.
Featured in
Higher-rated alternatives
open-compass/opencompass
OpenCompass is an LLM evaluation platform, supporting a wide range of models (Llama3, Mistral,...
IBM/unitxt
🦄 Unitxt is a Python library for enterprise-grade evaluation of AI performance, offering the...
lean-dojo/LeanDojo
Tool for data extraction and interacting with Lean programmatically.
GoodStartLabs/AI_Diplomacy
Frontier Models playing the board game Diplomacy.
google/litmus
Litmus is a comprehensive LLM testing and evaluation tool designed for GenAI Application...