CMU-SAFARI/Hermes
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
This project offers a specialized simulation framework to evaluate and develop new computer architecture designs aimed at speeding up how processors retrieve data. It takes detailed microarchitecture configurations and memory access traces as input, and outputs performance statistics and energy consumption metrics. Computer architects and hardware researchers would use this to model and test their innovative processor designs.
Use this if you are a computer architect or researcher working on novel processor designs and need to simulate the impact of speculative mechanisms on memory access latency and overall system performance.
Not ideal if you are looking for a general-purpose processor simulator without specific focus on speculative memory fetching or if you are not involved in hardware-level microarchitecture research.
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77
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13
Language
C++
License
MIT
Category
Last pushed
Feb 21, 2026
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