azwad-tamir/gpt_gnn_3D_partitioner
A GPT-GNN based verilog netlist partitioner for 3D IC design
This tool helps 3D IC designers partition complex digital circuit designs, described in Verilog, into multiple physical tiers. It takes a gate-level Verilog netlist, along with features like timing information and 2D placement data, and outputs a partitioned design ready for 3D IC physical implementation using conventional 2D design tools. This is ideal for integrated circuit designers working on advanced 3D chip architectures.
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Use this if you need to divide a gate-level Verilog netlist into distinct tiers for 3D integrated circuit physical design, especially when manual partitioning is too complex or time-consuming.
Not ideal if you are working with 2D IC designs or if you require a full-fledged 3D physical design and routing tool.
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Language
Verilog
License
MIT
Category
Last pushed
Jul 09, 2025
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