marcelwa/aigverse
A Python library for working with logic networks, synthesis, and optimization.
This project helps digital circuit designers and researchers efficiently build, optimize, and analyze logic networks. It takes specifications for logic circuits, often from existing files like Verilog or AIGER, and allows manipulation and optimization of these circuits as And-Inverter Graphs (AIGs). The output is an optimized logic network, which can also be converted into formats suitable for machine learning or data science analysis. Electrical engineers, computer architects, and hardware researchers would find this tool beneficial.
Available on PyPI.
Use this if you need to perform high-performance logic synthesis, optimize digital circuits, or convert complex logic designs into formats suitable for advanced analysis, all within a Python-first workflow.
Not ideal if you are solely doing high-level behavioral modeling or front-end hardware description without needing low-level logic synthesis or optimization capabilities.
Stars
74
Forks
4
Language
Python
License
MIT
Category
Last pushed
Mar 12, 2026
Commits (30d)
0
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