ryuz/BinaryBrain

Binary Neural Network Framework for FPGA(Differentiable LUT)

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Established

This project helps embedded systems engineers and researchers deploy highly efficient deep learning models directly onto FPGAs. It takes a description of your neural network and outputs Verilog code, which can then be used to configure an FPGA for tasks like real-time image recognition. The core innovation is directly training the FPGA's Look-up Table (LUT) elements for extremely low-latency, low-resource inference.

172 stars. No commits in the last 6 months. Available on PyPI.

Use this if you need to run deep learning inference with minimal hardware resources and ultra-low latency on an FPGA, especially for real-time applications like embedded vision systems.

Not ideal if you are looking to train and deploy complex, high-precision deep learning models on general-purpose GPUs or CPUs without specific FPGA hardware constraints.

FPGA development embedded AI hardware acceleration real-time inference deep learning deployment

Stale 6m No Dependents

Maintenance 2 / 25

Adoption 10 / 25

Maturity 25 / 25

Community 15 / 25

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Stars

172

Forks

Language

C++

License

MIT

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