ycchen218/EDA-Congestion-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.

29
/ 100
Experimental

This tool helps Electronic Design Automation (EDA) engineers identify potential routing congestion early in the chip design process. By taking placement information, macro region features, and pin density as input, it predicts specific locations on the chip where wiring might become overly dense and difficult to route. Chip designers can use this to proactively address congestion issues.

No commits in the last 6 months.

Use this if you are an EDA engineer looking for an early and fast prediction of routing congestion to guide your chip placement and routing strategies.

Not ideal if you need a detailed, physical routing simulation or are not working within the Electronic Design Automation domain.

chip-design electronic-design-automation VLSI routing-congestion placement-optimization
No License Stale 6m No Package No Dependents
Maintenance 0 / 25
Adoption 6 / 25
Maturity 8 / 25
Community 15 / 25

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Stars

24

Forks

5

Language

Python

License

Last pushed

Aug 28, 2024

Commits (30d)

0

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