ycchen218/EDA-DRC-Prediction

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.

28
/ 100
Experimental

This tool helps chip designers and layout engineers quickly identify potential Design Rule Check (DRC) violations in electronic circuit designs. By inputting design data, it predicts specific locations where manufacturing rules might be broken. This allows engineers to proactively address issues before physical fabrication.

No commits in the last 6 months.

Use this if you need to rapidly pinpoint areas in your electronic circuit layouts that are likely to fail Design Rule Checks, helping you accelerate the design iteration process.

Not ideal if you require a comprehensive design rule verification system that also performs rule correction, as this tool focuses solely on predicting violation locations.

electronic-design-automation chip-design semiconductor-manufacturing IC-layout-verification DRC-analysis
No License Stale 6m No Package No Dependents
Maintenance 0 / 25
Adoption 5 / 25
Maturity 8 / 25
Community 15 / 25

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Stars

13

Forks

4

Language

Python

License

Last pushed

Jun 24, 2023

Commits (30d)

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