NellyW8/VeriReason
This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
This project helps chip designers and verification engineers automatically generate Verilog Register-Transfer Level (RTL) code for hardware designs. It takes high-level design specifications or reasoning prompts as input and outputs optimized Verilog RTL code, which defines the circuit's behavior. This allows for faster and more accurate hardware design and synthesis.
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Use this if you need to generate high-quality, complex Verilog RTL code efficiently for digital circuit design and want to leverage advanced AI to enhance reasoning in code generation.
Not ideal if you are working with hardware description languages other than Verilog, or if your primary focus is on lower-level gate-level netlists rather than RTL code.
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Python
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Last pushed
Sep 25, 2025
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