jha-lab/acceltran

[TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers

40
/ 100
Emerging

AccelTran helps hardware designers evaluate custom accelerator designs for transformer models. You provide descriptions of a transformer model and an accelerator's architecture, and it simulates how that accelerator performs, including its area, power consumption, and how efficiently it uses its different parts. This is for hardware architects and researchers who are designing specialized chips for AI workloads.

No commits in the last 6 months.

Use this if you are designing custom hardware accelerators for transformer-based AI models and need to simulate and evaluate their performance and resource usage.

Not ideal if you are a software developer looking for a library to train or deploy transformer models, as this tool focuses on hardware architecture simulation.

AI-hardware-design chip-architecture VLSI-design neural-network-accelerators transformer-architecture
Stale 6m No Package No Dependents
Maintenance 0 / 25
Adoption 8 / 25
Maturity 16 / 25
Community 16 / 25

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Stars

58

Forks

10

Language

Python

License

BSD-3-Clause

Last pushed

Nov 22, 2023

Commits (30d)

0

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